1. Technical Field
The present invention pertains to oscillators. In particular, the present invention pertains to an oscillator with circuitry to increase the pulsewidth of an oscillator output pulse. Since the output pulse disables an oscillator current source, the increased pulsewidth of that pulse lengthens the time interval the current source maintains a disabled state, thereby reducing oscillator power consumption.
2. Discussion of Related Art
Nearly all electronic instruments employ some type of oscillator or waveform generator. A source of regular oscillation is necessary in any cyclical measuring device, such as one involving periodic states or waveforms. An oscillator may be used to provide a source of regularly spaced pulses or may be employed for stability and accuracy of resulting waveforms depending upon an application.
Although oscillators are a necessary component of any electronic device, oscillators consume significant amounts of power in various applications. This may be disadvantageous since power consumption has become a prominent consideration in most modern electronic devices, especially portable devices such as laptops, portable telephones, and personal data assistants.
In a typical oscillator, a current source is conducting during intervals between output pulses, where the output pulses are generally of short duration. Therefore, the oscillator is constantly consuming power for a majority of the time the oscillator is operating, thereby limiting the battery life of any handheld or portable devices that employ these types of oscillators. A conventional oscillator consuming power in this fashion is illustrated in FIG. 1. Specifically, a conventional oscillator 10 includes a current source 15, a capacitor 20 and a differential amplifier 30. The capacitor is disposed between current source 15 and a ground potential. Differential amplifier 30 includes a conventional configuration including a pair of n-channel field effect transistors (NFET) 22, 32 and a pair of p-channel field effect transistors (PFET) 24, 34. The sources of NFETs 22, 32 are tied together with a current source 23 disposed between the tied sources and a ground potential. The gates of PFETs 24, 34 are tied together and coupled to the drain of PFET 34. The drains of NFETs 22, 32 are respectively coupled to the drains of PFETs 24, 34. The gate of NFET 22 serves as the inverting input of the differential amplifier, while the gate of NFET 32 serves as the amplifier non-inverting input. The drain of NFET 22 provides the amplifier output. The differential amplifier basically produces a difference signal on the amplifier output representing the difference between signals provided to the non-inverting and inverting inputs.
The amplifier inverting input receives voltage from capacitor 20 (e.g., CAP as viewed in FIG. 1) and is coupled to a junction between the capacitor and current source 15. The amplifier non-inverting input is coupled to a reference voltage 60. Capacitor 20 receives current from current source 15 and charges accordingly. When the reference voltage exceeds the capacitor voltage, differential amplifier 30 produces a high level (e.g., positive potential) signal on the amplifier output. However, a low level (e.g., zero or negative potential) signal is produced by the differential amplifier in response to the capacitor voltage attaining at least the reference voltage. The amplifier output basically represents the difference between the capacitor and reference voltages. The output of differential amplifier 30 is coupled to a pair of transistors, PFET 55 and NFET 35, that control the output pulse of oscillator 10. In particular, the amplifier output is coupled to the gate of PFET 55, where the transistor source is tied to a ground potential and the transistor drain is tied to a drain of NFET 35. The source of NFET 35 is tied to a ground potential, while the transistor gate is coupled to reference voltage 60. PFET 55 drives the amplifier output signal, while NFET 35 controls the rate the pulse is pulled low as described below.
An inverter 40 is coupled to the junction between the drain of PFET 55 and the drain of NFET 35. The output of inverter 40 provides a signal to disable the current source during the output pulse as described below and is coupled to a subsequent inverter 45 that produces the oscillator output pulse (e.g., OUT as viewed in FIG. 1). Inverters 40 and 45 provide the oscillator output at a sufficient voltage to drive external circuitry, while providing the proper logic to maintain consistency between the logic states of the signal produced by transistors 35, 55 and the oscillator output signals.
An inverter 65 is disposed within a feedback path and is coupled to the output of inverter 40. Inverter 65 produces a high level signal in response to an oscillator output pulse (e.g., inverter 40 produces a low level signal in response to the oscillator output pulse which is inverted by inverter 65) to disable current source 15 during that pulse. The output of inverter 65 is coupled to a gate of an NFET 25. The NFET drain is coupled to the inverting input of differential amplifier 30, while the NFET source is tied to a ground potential. NFET 25 facilitates the discharge of capacitor 20 in response to the oscillator output pulse, thereby initiating a subsequent oscillator cycle to produce a successive pulse. A PFET 50 is disposed in the feedback path with the transistor gate coupled between inverters 40 and 65, the transistor source tied to a ground potential and the transistor drain coupled to the differential amplifier output. PFET 50 is enabled during an output pulse to disable PFET 55 and enable the pulse to be pulled low.
Operation of oscillator 10 is described with reference to FIGS. 1-2. Initially, capacitor 20 is discharged and provides a low level signal to the inverting input of differential amplifier 30 (e.g., CAP as viewed in FIGS. 1-2). Since the reference voltage provided to the amplifier non-inverting input exceeds the capacitor voltage, the differential amplifier produces a high level signal. This signal disables PFET 55, thereby producing a low level signal for the input of inverter 40. Inverter 40 inverts the low level signal and produces a high level signal for the feedback path and inverter 45. Inverter 45 inverts the high level signal and provides a low level signal as the oscillator output (e.g., OUT as viewed in FIGS. 1-2). The high level signal from inverter 40 traverses the feedback path and disables PFET 50. The signal is further received and inverted by inverter 65 to produce a low level signal that allows current source 15 to enter and/or maintain an enabled state and disables NFET 25, thereby enabling capacitor 20 to charge.
Current source 15 in an enabled state provides current to charge capacitor 20 as illustrated in FIG. 2. The oscillator operates as described above until the capacitor charges to at least the reference voltage. Once this occurs, the differential amplifier produces a low level signal that enables PFET 55. The combination of PFET 55 and NFET 35 produce an output pulse that is amplified by inverters 40 and 45 to form the oscillator output. This output pulse typically has a short duration (e.g., one to two percent of the oscillator period) as illustrated in FIG. 2. Since the output pulse is inverted by a pair of inverters, the resulting oscillator output logic level is equivalent to the logic level of the initial output pulse produced by the combination of transistors 35, 55.
Inverter 40 inverts the initial output pulse to provide a low level signal along the feedback path. The low level signal enables PFET 50 to disable PFET 55 and allow the signal generated by PFET 55 and NFET 35 to be pulled low. Inverter 65 inverts the low level signal to produce a high level signal that disables current source 15 during the output pulse and enables NFET 25 to discharge capacitor 20 as illustrated in FIG. 2.
Once the capacitor voltage falls below the reference voltage (e.g., due to the discharge), differential amplifier 30 produces a high level signal as described above. Subsequently, the output produced by the combination of transistors 35, 55 returns to a low level and inverters 40 and 45 produce a low level oscillator output as described above. Inverter 40 inverts the low level output signal and generates a high level signal along the feedback path that disables PFET 50. Inverter 65 receives the high level signal and produces a low level signal that enables the current source and disables NFET 25 to permit capacitor 20 to charge. The enabled current source charges the capacitor to produce a subsequent oscillator output pulse as described above. Thus, since current source 15 of oscillator 10 is disabled during the small time interval corresponding to the output pulsewidth, the current source is enabled virtually the entire time the oscillator is operating, thereby consuming a significant amount of power.